Such a circuit can be used, for example, in voltage controlled oscillators (VCOs), where the resonant circuit may, for example, contain a varactor, by means of which the resonant frequency of the tuned circuit can be adjusted. An essential criterion for the proper function of a voltage controlled oscillator is its phase noise. Up to now, these oscillator circuits tended to use MOS-FETs as current-defining elements, that is as current sources. An NMOS-FET is used in most cases, the current of which is defined by means of a current mirror in combination with a band separation reference voltage generating circuit. A disadvantage of using MOS-FETs is their suscectivity to I/f noise, in particular at low frequencies, which in such VCOs then has a material influence on the phase noise of the VCO. The I/f noise is hereby proportional to the gate surface of the MOS-FET (WxL). In the case of semiconductor manufacturing processes for the production of digital and VCO containing PLL circuits, which are used at present, and where the gate length of the MOS-FET is smaller than 0.2 micrometers, the I/f noise of the MOS current source therefore constitutes the decisive influence on the phase noise of the VCO. This influence of the I/f noise becomes even greater if bonded wires are used as the inductances of the LC resonant circuit of the oscillator circuit, which are much liked in such applications because of their high Q factor, and even then contribute very little to the phase noise of the VCO.
Several attempts have been made so far to reduce the influence of I/f noise of MOS-FETs in oscillator circuits.
In an article “Reducing MOS-FET I/f noise and power consumption by switched biasing” by Eric A. M. Klumperink et. al. in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol 35, issue 7th Jul. 2000, a MOS transistor is described as a current source in an oscillator circuit that is alternately operated in either its “strong inversion” or in its saturation state, whereby the source-gate voltage is switched back and forth between different values, in order to minimize the I/f noise of the MOS transistor. But the I/f noise in this case cannot be completely eliminated, because the MOS transistor that is used as a current source still contributes to the I/f noise to a considerable extent, as can be appreciated in FIG. 3 of the publication.
An afore-mentioned oscillator circuit is described for example in the article “A packaged 1.1 GHz CMOS VCO with phase noise of −126 dBc/Hz at a 600 kHz offset” by C.-M. Hung and Kenneth K. O. in the IEEE JOURNAL OF SOLIDSTATE CIRCUITS, Vol. 35, Issue No. 1, 1 Jan. 2000, page 100 and following, and represented in FIG. 1 of that publication. The circuit described obtains a reduction of the phase noise, among other factors, by the use of several inductances that are located on the chip. A disadvantage of this type of oscillator consists in an increased use of space caused by the additional inductances. The current source of this oscillator furthermore makes use of a PMOS FET with buried channel, in order to achieve a further I/f noise reduction. However, since MOS FETs are still being used, considerable I/f noise can still be expected, as is represented in FIG. 3 of the publication.